We speak a whole lot about course of action nodes at ExtremeTech, but we do not generally refer back again to what a course of action node technically is. With Intel’s 10nm node now in generation and TSMC + Samsung speaking about potential 5nm nodes, it is a great time to revisit the topic, specifically the issue of how TSMC and Samsung evaluate to Intel.
Method nodes are ordinarily named with a quantity adopted by the abbreviation for nanometer: 32nm, 22nm, 14nm, and many others. There is no set, goal romantic relationship concerning any element of the CPU and the identify of the node. This was not always the circumstance. From approximately the 1960s by way of the conclusion of the 1990s, nodes were being named based on their gate lengths. This chart from IEEE displays the romantic relationship:
For a very long time, gate length (the length of the transistor gate) and half-pitch (half the distance concerning two similar functions on a chip) matched the course of action node identify, but the very last time this was genuine was 1997. The half-pitch ongoing to match the node identify for many generations but is no for a longer time linked to it in any sensible sense. In truth, it is been a very very long time because our geometric scaling of processor nodes essentially matched with what the curve would glance like if we’d been capable to go on essentially shrinking element measurements.
If we’d strike the geometric scaling specifications to preserve node names and true element measurements synchronized, we’d have plunged down below 1nm producing 6 several years ago. The numbers that we use to signify each new node are just numbers that corporations pick. Back in 2010, the ITRS (far more on them in a moment) referred to the technological innovation chum bucket dumped in at every single node as enabling “equivalent scaling.” As we strategy the conclusion of the nanometer scale, corporations might get started referring to angstroms instead of nanometers, or we might basically start applying decimal points. When I commenced get the job done in this marketplace it was significantly far more widespread to see journalists refer to course of action nodes in microns instead of nanometers — .18-micron or .13-micron, for instance, instead of 180nm or 130nm.
How the Sector Fragmented
Semiconductor producing requires tremendous capital expenditure and a great deal of very long-time period study. The regular length of time concerning when a new technological strategy is released in a paper and when it hits widescale professional producing is on the order of 10-15 several years. Decades ago, the semiconductor marketplace acknowledged that it would be to everyone’s benefit if a general roadmap existed for node introductions and the element measurements those people nodes would target. This would enable for the wide, simultaneous progress of all the pieces of the puzzle necessary to bring a new node to marketplace. For many several years, the ITRS — the Global Engineering Roadmap for Semiconductors — posted a general roadmap for the marketplace. These roadmaps stretched above 15 several years and set general targets for the semiconductor marketplace.
The ITRS was posted from 1998-2015. From 2013-2014, the ITRS reorganized into the ITRS 2., but before long acknowledged that the scope of its mandate — specifically, to give “the key reference into the potential for university, consortia, and marketplace scientists to encourage innovation in several regions of technology” necessary the organization to significantly expand its attain and coverage. The ITRS was retired and a new organization was shaped termed IRDS — Global Roadmap for Devices and Programs — with a significantly much larger mandate, covering a wider set of technologies.
This change in scope and concentration mirrors what’s been taking place across the foundry marketplace. The motive we stopped tying gate length or half-pitch to node dimension is that they possibly stopped scaling or commenced scaling significantly far more little by little. As an choice, corporations have integrated several new technologies and producing techniques to enable for ongoing node scaling. At 40/45nm, corporations like GF and TSMC released immersion lithography. Double-patterning was released at 32nm. Gate-very last producing was a element of 28nm. FinFETs were being released by Intel at 22nm and the rest of the marketplace at the 14/16nm node.
Corporations from time to time introduce functions and capabilities at unique instances. AMD and TSMC released immersion lithography at 40/45nm, but Intel waited right until 32nm to use that system, opting to roll out double-patterning to start with. GlobalFoundries and TSMC commenced applying double-patterning far more at 32/28nm. TSMC employed gate-very last building at 28nm, while Samsung and GF employed gate-to start with technological innovation. But as development has gotten slower, we have noticed corporations lean far more greatly on internet marketing, with a bigger array of described “nodes.” As a substitute of waterfalling above a relatively significant numerical area (90, 65, 45) corporations like Samsung are launching nodes that are ideal on leading of each other, numerically talking:
I imagine you can argue that this product tactic isn’t very obvious, due to the fact there is no way to inform which course of action nodes are evolved variants of previously nodes unless of course you have the chart handy.
Even though node names are not tied to any precise element dimension, and some functions have stopped scaling, semiconductor suppliers are continue to finding strategies to make improvements to on important metrics. Which is genuine engineering enhancement. But due to the fact benefits are more challenging to arrive by now, and just take for a longer time to establish, corporations are experimenting far more with what to call those people enhancements. Samsung, for instance, is deploying many far more node names than it employed to. Which is internet marketing.
Why Do Men and women Declare Intel 10nm and TSMC/Samsung 7nm Are Equal?
Mainly because the producing parameters for Intel’s 10nm course of action are very close to the values TSMC and Samsung use for what they call a 7nm course of action. The chart down below is drawn from WikiChip, but it brings together the identified element measurements for Intel’s 10nm node with the identified element measurements for TSMC’s and Samsung’s 7nm node. As you can see, they’re very comparable:
The delta 14nm / delta 10nm column displays how significantly each firm scaled a specific element down from its earlier node. Intel and Samsung have a tighter bare minimum steel pitch than TSMC does, but TSMC’s significant-density SRAM cells are more compact than Intel’s, probable reflecting the requires of unique consumers at the Taiwanese foundry. Samsung’s cells, in the meantime, are even more compact than TSMC’s. Total, even so, Intel’s 10nm course of action hits many of the important metrics as what both of those TSMC and Samsung are calling 7nm.
Specific chips might continue to have functions that depart from these measurements due to specific structure goals. The information and facts suppliers give on these numbers are for a standard envisioned implementation on a specified node, not necessarily an precise match for any precise chip.
There have been queries about how intently Intel’s 10nm+ course of action (employed for Ice Lake) displays these figures (which I believe that were being posted for Cannon Lake). It is genuine that the expect technical specs for Intel’s 10nm node might have modified a little bit, but 14nm+ was an adjustment from 14nm as perfectly. Intel has said that it is continue to concentrating on a 2.7x scaling factor for 10nm relative to 14nm, so we’ll maintain off on any speculation about how 10nm+ might be a little bit unique.
Pulling It All Together
The greatest way to recognize the which means of a new course of action node is to imagine of it as an umbrella time period. When a foundry talks about rolling out a new course of action node, what they are indicating boils down to this:
“We have designed a new producing course of action with more compact functions and tighter tolerances. In order to obtain this purpose, we have integrated new producing technologies. We refer to this set of new producing technologies as a course of action node due to the fact we want an umbrella time period that makes it possible for us to capture the concept of development and improved capability.”
Any additional queries on the topic? Fall them down below and I’ll respond to them.